ASIC RTL Design Engineer - Memory PHY
Dexian DISYS · Boxborough, Middlesex County
$123,836 per year · Full-Time · Posted 10 hours ago
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About the job
ASIC RTL Design Engineer - Memory PHY Boxborough, MA (Hybrid) 12 Months Must have strong ASIC/Digital Design, RTL Coding (Verilog/SystemVerilog), C/C++, Synthesis, Timing Closure, and CDC experience. Plus: DDR/LPDDR, Memory PHY, high-speed interface design, and Python/TCL scripting. Dexian stands at the forefront of Talent Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional …
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